Abstract— The paper presents an algorithm of 2.5D X-clock tree synthesis based on the stacked-layer combination of voltage islands for reducing both power consumption and clock delay. Double via insertion is also considered for via-effect avoidance and reliability. The algorithm can reduces the complexity of 3D clock tree construction of a stacked-layer chip. A clock network is first partitioned into the number of voltage islands distributed on each layer, such as L-type and T-type, and the X-clock tree is constructed for each voltage island. Then, we integrate these X-clock trees based on a well-defined connection each layer by inserting level shifters and TSVs for minimizing the power with the best trade off in power and delay. Experimental results show that our approach can save up to 10.94% and 35.185% effectively on average in power and delay, respectively.
Keywords— X-clock tree, stacked layer, voltage island, level shifter, double via, clock delay, power consumption.
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