An Efficient Voltage and Frequency Division Methods for Multiprecision Multiplier on FPGA

Abstract In this paper, we present a reconfigurable multiprecision(MP) multiplier that contains variable precision ,parallel processing, Dynamic voltage scaling (DVS)and dedicated MP operands scheduling to provide desired performance for various operating conditions. The proposed reconfigurable multiplier works independent smaller precision also it works in parallel to perform higher precision multiplications according to conditions or user requirements of voltage or frequency the dynamic voltage/frequency scaling unit configures to works at proper precision and frequency. In this paper we design a multiplier circuit that consumes less power and reduces area overhead by parallel processing .for this instead of using 16bit or 32bit operands we used single 8bit or twin parallel bit multiplication operation . in multipresicion multiplier small multiplications causes complex structures which results in unwanted signal generation and increases complexity of circuitary ,for this we used 8bit multiplier for 16 bit and 32bit multiplication hence to reduce power consumption and acconding to runtime workload we combine multiprecision multiplier with dynamic voltage scaling(DVS).The DVS technique consists look up tables(LUT) and on chip critical path replica approach .The LUT allows the supply voltage according to the voltage frequency relationship stored in LUT.

Keywords Multiprecision, Reconfigurable.

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An Efficient Voltage and Frequency Division Methods for Multiprecision Multiplier on FPGA

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