Abstract— With the remarkable scaling down of technology, test engineers are encountered with new challenges. With the reduction technology moving down to Deep Submicron level, the digital designs are moving closer to the probability of defects related to time. The traditional Stuck-at tests and IDDQ tests can no more detect few distinctive faults which may be occurring due to issues related to timing of the signal. The defect spectrum is thus broadened by the inclusion of other types of faults such as high impedance shorts, in-line resistance, and cross-talk between signals. This paper proposes the use of At-Speed test which is better suited to detect the new types of failures that occur in a digital circuit due to its complex design. The use of At-speed test ensures the timing reliability of the chip after manufacturing thereby reducing DPM (Defect per million) rate. At-speed tests when added with the traditional stuck-at tests, guarantees maximum fault coverage and reduced DPM rates (@30 to 70%). Though At-speed testing is not a new concept and few ASIC vendors have been using this, they have been using functional test patterns to create them which are a very tedious and time consuming routine. Diagnosing the failure source also becomes difficult with the failure of functional patterns. This paper discusses about the fault models provided by industries leading ATPG tools that targets the At-speed failure.
Keywords— At-Speed test, functional test patterns, fault coverage, Stuck-At-Test, IDDQ Tests.
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