Abstract— The adder is most commonly used arithmetic block of CPU (central processing unit) and DSP (digital signal processing), therefore its power and performance optimization is very important. With the scaling of technology to deep submicron, the speed of the circuit increases rapidly. At the same time, the power consumption per chip also increases significantly due to increasing density of the chip. Therefore, in realizing modern VLSI circuits, low power and high speed are the two predominant factors which need to be considered. In this work, there is try to determine the best solution to this problem by improving the performance of adders.
In this work, we improve and compare the power consumption of the three adders. The conventional full adder is built by 28 transistors. So, the transistor count is very high. The average power consumption and delay are very high. In this work, we consider three types of 64-Bit adders and try to improve their performance by varying width and length of substrate. For this purpose, we use tanner tool.
Keywords— CSL, CPL, DPL, Low power design.
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